Career
Valley Spring Semiconductor

Talent
recruitment

Email: hr@valleyspringsemi.com

Our team is in search of 3 Senior Analog Design Engineers and 3 Analog Design Engineers to spearhead the creation of analog mixed-signal circuits for high performance timing clock ICs. The successful candidates will participate in designing Analog or Digital PLL circuits for ultra-low jitter clock ICs. They will need to guide layout design, perform and manage prototype evaluation and debugging, and engage in the complete chip design process.

  • RESPONSIBILITIES:

    Design Analog or All Digital PLL circuits, including Charge Pump, MMD, VCO; or related modules such as TDC, DTC, DCO, PI，etc.
    Develop high performance basic analog circuit modules, including Bandgap, LDO，High Speed Differential Buffer .
    Model module-level behavioral models, execute mixed-signal verification and testing.
    Understand the chip architecture and participate in system verification. Lead and participate in layout design.
    Perform and manage prototype evaluation and debugging.

  • MINIMUM REQUIREMENTS:

    Master's or Bachelor’s degree in Electrical Engineering with 5+ years of relevant experience.
    Profound understanding of analog mixed-signal design, preferably with experience in high performance timing clock ICs.
    Comprehensive understanding and experience in designing analog mixed-signal circuit including PLL, phase interpolator, low jitter clock, LDO, high-speed ADC.
    Hands-on experience with IC development from definition to high-volume production, including layout supervision, bench evaluation, correlation, and characterization.